An electronic device may comprise a plurality of components mounted to a printed circuit assembly (such as, e.g., a single or multilayer fiberglass printed circuit board (PCB), a single or multilayer ceramic PCB). The printed circuit assembly may include patterns of conductive elements (e.g., pads, traces, and/or planes) to interconnect the components in a predetermined way.
For some semiconductor components, a plurality of terminations on the surface of a die are interconnected to form a component terminal. An example of such a component is a power MOSFET, which can include a plurality (in some cases many thousands) of active cells, each cell comprising a drain, source and gate termination. The drain terminal of the component can be formed by connecting essentially all of the drain terminations of the active cells together. Likewise, the source and gate terminals can be formed by connecting essentially all of the source and gate terminations of the active cells together.
“Lateral” power MOSFET devices may include a plurality of active cells comprising drain, source, and gate terminations. However, unlike a “vertical” MOSFET, which has the drain and source terminations of individual cells disposed on opposite surfaces of a die, all of the gate, source, and drain terminations of the cells of a lateral MOSFET may reside on a single surface of the die.
Semiconductor components may be mounted directly to a printed circuit assembly. One way to do this, shown in FIGS. 1A and 1B, is to directly connect conductive pads (e.g., pads 10a, 10b, 10c) on the surface of the printed circuit assembly 12 to interconnection pads (not shown) on the surface of a semiconductor die 14 by use of area array interconnects (e.g., ball-grid array interconnects 16a, 16b, and 16c). The area array interconnects may be made, e.g., of solder or conductive epoxy. Stud bumps may also be used. The assembly method shown in FIG. 1 is sometimes referred to as a “flip-chip” assembly.
Connecting a lateral MOSFET die to a printed circuit assembly using a flip-chip assembly technique presents unique problems if low-impedance source and drain connections are desired. One way to make low electrical impedance connections between such a device and a printed circuit assembly is discussed in Vinciarelli et al, U.S. Pat. No. 7,038,917, “Low Loss, High Density, Array Interconnection,” assigned to VLT, Inc. of Sunnyvale, Calif. and incorporated by reference in its entirety (the “Array Patent”). Another way to interconnect a plurality of connections disposed on the same side of a die is described with respect to a voltage regulator integrated circuit in Burstein et al., U.S. Pat. No. 6,278,264, “Flip-Chip Switching Regulator.”
Another way to connect a semiconductor die to a printed circuit assembly is to pre-assemble the die into a package having terminal connections and solder the terminal connections to pads on the surface of the printed circuit assembly. Examples of such package embodiments include D-Pak, DirectFET and Power QFN packages manufactured by International Rectifier Corporation, El Segundo, Calif. 90245, USA; and LCC1, SMD1, SMD2 and SMD05 packages manufactured by TTElectronics Semelab, Lutterworth Leicestershire, UK. Another example of a power semiconductor package is found in Moline, U.S. Pat. No. 5,075,759, “Surface Mounting Semiconductor Device and Method”. Recommended pad layouts for a package of this kind are illustrated in Application Note AN-1136, “Discrete Power Quad Flat Pack No-Leads (PQFN) Board Mounting Application Note,” Version 1.0, June 2008, published by International Rectifier Corporation, El Segundo, Calif. 90245, USA. Examples of semiconductor packages that comprise a multilayer substrate as part of the package are described in Eden et al, U.S. Pat. No. 6,710,441, “Power Semiconductor Switching Devices . . . ” and in Pace, U.S. Pat. No. 5,904,499, “Package for Power Semiconductor Chips.”